1. Field of the Invention
The present invention generally relates to a Pseudo Static Random Access Memory (hereinafter, referred to as “PSRAM”), and more specifically, to a PSRAM for performing a Write-Verify-Read (hereinafter, referred to as “WVR”) function at a test mode to easily analyze defects.
2. Description of the Prior Art
Generally, a Dynamic Random Access Memory (hereinafter, referred to as “DRAM”) memorizes information with charges in a cell capacitor, transmits accumulative charges to a corresponding bit line through an access transistor, and reads data amplified by a sense amplifier.
Since a memory cell of the DRAM that comprises one access transistor and one cell capacitor occupies a small area, a memory of high capacity can be embodied with the small area.
FIG. 1 is a timing diagram illustrating the operation of a conventional DRAM for performing a WVR function.
Referring to FIG. 1, after a word line WL corresponding to a row address RADD is activated by a command /RAS, a write command WR and a read command RD are successively inputted to the same column address CADD in response to a command /CAS and a write active command /WE. Then, a column operation is successively performed while the word line WL is activated. In this way, the WVR function is performed.
Meanwhile, a memory device becomes smaller for high-speed operation of the memory device, reduction of consumed current and miniaturization of the processing system. As the memory device becomes smaller, a memory cell capacitor also becomes smaller so that capacity of the memory cell capacitor is reduced. As a result, the amount of retention charges becomes smaller although data having the same voltage level are inputted to the capacitor.
In order to compensate the reduction in the amount of retention charges, a refresh operation is periodically performed. In the refresh operation, data stored in the memory cell capacitor are transmitted to a bit line, amplified in a sense amplifier, and then re-written in the memory cell capacitor.
As a result, when data retention characteristics are degraded in the miniaturized device, a refresh cycle is required to be set short in order to compensate the degradation of the data retention characteristics. However, when the refresh cycle is set short, an external processing unit cannot access the DRAM during the refresh operation, thereby degrading the performance of the processing system. Additionally, the amount of consumed current for performing the refresh operation increases when the refresh cycle becomes short. The short refresh cycle does not satisfies the low standby current condition required in a data retention mode of battery driving portable devices, and is not applied to the battery driving portable devices which require low power consumption.
In order to solve the problem of the refresh operation in the DRAM, a PSRAM has been used to operate the DRAM as a SRAM. In the PSRAM, a cycle for reading and writing data and a refresh cycle for performing a refresh operation are successively performed in one of memory access cycles. In other words, since the refresh operation is performed in one access cycle, the refresh can be hidden to the external access so that the DRAM may be operated as the SRAM seemingly.
FIG. 2 is a timing diagram illustrating the operation of a conventional PSRAM for successively performing write and read operations.
Referring to FIG. 2, when row and column addresses ADD are simultaneously inputted, the word line WL activated at the write mode is automatically precharged if the write active command /WE is inactivated to the high level. Then, the word line WL is activated and the read operation RD is performed. As a result, the WVR function for performing only the column operation while the word line WL is activated cannot be performed.
In other words, since the PSRAM does not have the precharge command, a self-refresh operation is performed at the read mode. The PSRAM performs the precharge operation when the write active signal /WE or the chip selecting signal /CS is inactivated to a high level at the write mode WR.
Since a row address and a column address are simultaneously inputted like in the DRAM, the WVR function for alternately performing write WR and read RD operations cannot be performed while the word line WL is activated in the conventional art.